Clock networks of programmable logic devices (“PLDs”), such as Field Programmable Gate Arrays (“FGPAs”) for example, have used regional and global clocks. Conventionally, such regional clocks were driven only from an “edge” of such PLDs, and such global clocks were driven only from the center of such PLDs. This type of clock network architecture was considerably inflexible. However, as PLDs became larger, clock skew and/or clock delay, as well as increased timing uncertainty, became more of an issue, and such inflexibility made addressing one or more of these issues more problematic. Hence, it is desirable and useful to provide an IC that has more flexibility to reduce one or more of these issues.